PICMG 1.3 allows users to protect their investment in PCI (PCI-X) technology while taking advantage of the speed and increased bandwith of PCI Express.

What is PICMG 1.3?

  • Bringing PCI Express to your SBC increased speed and bandwidth

    Designed to interface with PCI Express peripherals on a backplane. The PCI Express interconnects with the backplane and can operate at x1, x4, x8, x16, and more depending on the capabilities of both the SHB and the backplane.

  • Support PCI (PCI-X) on board with flexibility

    The optional PCI (PCI-X) portion on the SHB interconnect with the backplane allows for 32-bit operation. The clock rate can be 33MHz, 66MHz, 100MHz, and 133MHz, depending on how the backplane and SHB are designed.

  • Miscellaneous I/O

    SATA, USB, IPMB, SMBUS, Geographic Addressing, and PCI Wake Up to the backplane is specified. Simplified the cabling on SHB for the system

PICMG 1.3 Key Features

  • PCI Express

    20 PCI Express lanes including x16, x4, and x1 PCI Express configuration are supported

  • Reset signal line defined

    Common header defined on backplane for reset function

  • ATX power signals are supported

    AUX voltages for stand-by power and sleep states (Soft starts, wake-on-LAN). Supports PSON#, PWRGD, PWRRBT#, and ACPI states.

Why PICMG 1.3?

  • This new technology is expected to allow PCIe transmission rates to keep pace with processor and I/O advances for the next 10 years or more.
  • Same basic mechanical dimensions are maintained to minimize chassis redesign expense.
  • Better host board power management and simplified I/O cabling
  • Supports PCI Express and PCI option cards without driver changing